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1/30 STA304 january 2002 this is preliminary information on a new product foreseen to be developed. details are subject to change without notice. n end to end digital audio integrated solution n dsp functions: - digital volume control - soft mute - bass and treble - parametric eq per channel - bass management for subwoofer - auto mute on zero input detection n 4+1 direct digital amplification (ddx?) output channels n 6 channels programmable serial output interface (by default i2s) n 4 channels programmable serial input interface (by default i2s) n stereo s/pdif input interface n intel ac'97 link (rev. 2.1) input interface for audio and control n on chip automatic input sampling frequency detection n 100 db snr sample rate converter (1khz sinusoidal input) n i 2 c control bus n low power 3.3v cmos technology n embedded pll for internal clock generation (1024x48 khz = 49.152 mhz) n 24.576 mhz external input clock or built-in industry standard xtal oscillator. 1.0 description the STA304 digital audio processor is a single chip device implementing end to end digital solution for audio application. in conjunction with sta500 power bridge it gives the full digital dsp-to-power high qual- ity chain with no need for audio digital-to-analog con- verters between dsp and power stage. tqfp44 ordering number: STA304 product preview digital audio processor with multichannel ddx? block diagram dsp src i2s ac`97 s/pdif ddx i2s pll i2c reset lrcki / sync sdi_1 / sdata_out sdi_2 / sdata_in rxp rxn bicki / bit_cl sdo_1 sdo_2 sdo_3 lrcko bicko xti xto left_b left_a right_b right_a sleft_a sleft_b sright_a sright_b lfe_a lfe_b scl sda sa ram rom ckout 18 1 2 3 4 19 11 10 9 7 14 15 43 43 43 43 43 43 22 21 24 23 34 33 28 27 30 29 powerdown 44 35 eapd pwdn
STA304 2/30 1.0 description (continued) the device supports two main configurations as far as input sources: ac'97 input or iis/spdif input: selection is made via a dedicated pin ( ac97_mode pin). the ac`97 can be configured to work in two different ways: 'full compliant' mode and 'proprietary' mode which enables more features. the selection of the operating mode is done via a specific bit in a vendor reserved register (see bit 0: ac97_fc_mode in the cra register, address 5ah). the 'full compliant' mode is compliant with rev. 2.1 of ac`97 link specifications. this link can provide up to 6 input audio channels with sampling frequency of 44.1, 48, 88.2, 96 khz, and the related controls. in the iis/spdif mode, a stereo s/pdif and a 4 channels three-wires programmable serial input interface work in mutually exclusive way. two channels with sampling frequency in the continuous range from 32 to 96 khz are supported by the s/pdif interface. up to four channels with sampling frequency varying continuously from 32khz up to 96 khz are supported by the programmable serial interfaces. among the different configurations, also the standard iis protocol is supported. an embedded high quality sample rate converter (src) resamples input data at the internal fixed sampling fre- quency of 48 khz for dsp operations. the dsp is a 20x20 bit core audio processor performing several user controlled parametric algorithms, among them are dynamic and static equalization, bass, treble, volume control and more. the dsp operates at 49.152mhz (1024xfs). this frequency is generated by an internal pll with programmable multiplication factor (x2 or x8). this device has 5 channels direct digital amplification (ddx? technology), performing high efficiency class-d pwm output signals used to drive directly external power bridge stages (sta500). in addition a 6 channel digital output programmable interface (supporting iis standard protocol) is embedded for applications with commercial audio d/a converters. the output sampling frequency is fixed at 48 khz when the interface operates as master. in addition an oversampled clock (256xfs or 512xfs) is provided externally for the d/a converters. an iic interface allows full programmability of internal algorithms and control registers via an external controller. an arbitration logic handles access conflicts to embedded control registers (which may occur as a consequence of contemporary access to control registers by aclink, iic and dsp blocks). figure 1. dsp data processing bass redir . volume ctrl. l, r, sl, sr, lfe, cnt cnt i2s + ddx i2s l, r, sl, sr, lfe center volume ctrl. static & dinamic eq
STA304 3/30 pin connection (top view) pin function pin name type description pad type 1 sdi_1 / sdata_out i input i2s serial data 1 / ac97 output data cmos schmitt in 2 sdi_2 / sdata_in i/o input i2s serial data 2 / ac97 input data cmos in / cmos out 2ma 3 lrcki / sync i/o input i2s left/right clock / ac97 synch. clock cmos in / cmos out 2ma 4 bicki / bit_clk i/o input i2s serial clock / ac97 bit clock cmos in / cmos out 4ma 5 vdd_1 digital supply voltage 6 gnd_1 digital ground 7 reset i global reset (this pin is sensed only after 2 clock cycles) cmos schmitt in pull-up 8 ac97_mode i ac97 enable / disable (1=ac97; 0=i2s/ spdif) cmos schmitt in pull-down 9 sda i/o i2c serial data cmos in / cmos out 2ma 10 scl i i2c serial clock cmos in 11 sa ac97 primary/secondary codec selector cmos in 12 test_mode i test mode (active high) cmos 13 vdd_2 digital supply voltage 14 xti i crystal input (clock input) analog in 15 xto o crystal output cmos out oscill. pad 16 gnd_2 digital ground 1 2 3 5 6 4 7 8 9 10 17 11 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 28 27 26 24 23 25 33 32 31 29 30 sdi_1/sdata_out sdi_2/sdata_in lrcki/sync bicki/bit_clk vdd_1 gnd_1 reset ac97_mode sda scl sa test_mode vdd_2 xti xto gnd_2 vcc rxp rxn vss lfe_b lfe_a sleft_a eapd lrcko sdo_1 sdo_2 sdo_3 scko gnd_5 vdd_5 ckout pwdn sright_b sright_a gnd_3 vdd_3 right_b right_a left_b left_a gnd_4 vdd_4 sleft_b d00au1160 12 13 14 15 16
STA304 4/30 pin name type description pad type 17 vcc analog supply voltage 18 rxp i s/pdif receiver positive analog in 19 rxn i s/pdif receiver negative analog in 20 vss analog ground 21 lfe_b o pwm lfe (subwoofer) output channel (b) cmos out 3ma 22 lfe_a o pwm lfe (subwoofer) output channel (a) cmos out 3ma 23 sright_b o pwm surround right output channel (b) cmos out 3ma 24 sright_a o pwm surround right output channel (a) cmos out 3ma 25 gnd_3 digital ground 26 vdd_3 digital supply voltage 27 right_b o pwm right output channel (b) cmos out 3ma 28 right_a o pwm right output channel (a) cmos out 3ma 29 left_b o pwm left output channel (b) cmos out 3ma 30 left_a o pwm left output channel (a) cmos out 3ma 31 gnd_4 digital ground 32 vdd_4 digital supply voltage 33 sleft_b o pwm surround left output channel (b) cmos out 3ma 34 sleft_a o pwm surround left output channel (a) cmos out 3ma 35 eapd o external amplifier powerdown (active low) cmos out 2ma 36 lrcko i/o output i2s left/right clock cmos in / cmos out 2ma 37 sdo_1 o output i2s serial data 1 cmos out 2ma 38 sdo_2 o output i2s serial data 2 cmos out 2ma 39 sdo_3 o output i2s serial data 3 cmos out 2ma 40 scko i/o output i2s serial clock cmos in / cmos out 4ma 41 gnd_5 digital ground 42 vdd_5 digital supply voltage 43 ckout o clock output (12 /24 mhz) cmos out 8ma 44 pwdn i device powerdown (active low) cmos in pull-up pin function (continued)
STA304 5/30 absolute maximum ratings thermal data electrical characteristcs (v dd from 2.9v up to 3.4v; t amb = 0 to 70 c; unless otherwise specified) dc operating conditions general interface electrical characteristics note 1: the leakage currents are generally very small, < 1na. the value given here is a maximum that can occur after an electro static stress on the pin. note 2: human body model symbol parameter value unit v dd power supply -0.3 to 4 v v i voltage on input pins -0.3 to vdd+0.3 v v o voltage on output pins -0.3 to vdd+0.3 v t stg storage temperature -40 to +150 c t op operative ambient temperature -20 to +85 c p dd power consumption digital tbd mw p da power consumption analog tbd mw symbol parameter value unit r thj-amb thermal resistance junction to ambient 85 c/w symbol parameter value v dd power supply voltage 3.0 to 3.6v t j operating junction temperature -20 to 125 c symbol parameter test condition min. typ. max. unit note i il low level input current without pull-up device v i = 0v -10 10 m a1 i ih high level input current without pull-up device v i = v dd = 3.6v -10 10 m a1 v esd electrostatic protection leakage < 1 m a2000 v2
STA304 6/30 dc electrical characteristics 2.0 ac97 bank register overview the ac `97 interface is compliant to audio codec `97 C revision 2.1 specification, as far as the protocol used. all the registers described in this specification, including standard, vendor reserved and extended audio (ac `97 2.0) registers, are available in this device, but just relevant registers which are described in paragraph 11 (register summary) are implemented. the ate mode feature has been implemented for test purpose: for related details refer to the audio codec `97 C revision 2.1 specification. 2.1 reading ac `97 registers since the ac`97 register bank has been implemented as a contiguous ram space (from a dsp point of view) the content of the ram itself will be returned as the result of a read operation. this should be followed as a general rule of thumb but, where not possible, a different approach has been used. hereby is a list of the reg- isters, and bits, that do not follow this rule or that have a particular handling: ? codecid_0, codecid_1 : these two bit are respectively bits 14 and 15 of registers 28h (extended audio id) and 3ch (ewxtended modem id). when a read operation of these registers is performed the returned value is based on the status of the sa pin: codecid_0 report the status of sa pin, codecid_1 always report 0. other bits of these regis- ters return the related ram register contents. also note that the status of the sa pin is not readable by the dsp. ?pr4 : the bit 12 of register 26h (powerdown, ctrl/start) is used to set the ac`97 bit_clk and sdata_in signal to a low state. in response to a warmers the status of this bit is set back to its default 0 value. in response symbol parameter test condition min. typ. max. unit note v il low level input voltage 0.2*v dd v v ih high level input voltage 0.8*v dd v v ol low level output voltage iol = x ma 0.4*v dd v 1,2 v oh high level output voltage 0.85*v dd v 1,2 note 1: takes into account 200mv voltage drop in both supply lines note 2: x is the source/sinc current under worst case conditions and is reflected in the name of the i/o cell according to the drive capability. i pu pull-up current v i = 0v; v dd = 3.3v -25 -66 -125 m a1 r pu equivalent pull-up resistance 50 k w t r reset active time 2t ck ns t ck master clock period ns note 1: min condition: v dd = 3.0v, 125c min process; max. condition: v dd = 3.6 v, -20c max process. digital characteristics-spdif receiver (rxp,rxn pins only, spdif - mode = analog) zin input resistance k w vth dufferential input voltage 200 mv vhy input hysteresis 50 mv 1 49.152 ----------------- -
STA304 7/30 to a read request the actual value of this signal is returned, not the ram content. due to this fact the relative ram register content can be incongruous. ? regs . 2ch, 2eh and 30h (audio sample rate control): these three registers are used to setup the sample rate when the variable rate mode is enabled. in re- sponse to a read request on one of these registers the actual value returned can be either bb80h or ac44h, depending on the status of an internal hardware signal; the status of this signal is updated every time a write operation into one of these register is performed. for more details regarding a specific bit please refer to the appropriate paragraph. in order to be as much compliant to the specification as possible two different mode of operation has been in- troduced. using the ac97_fc_mode configuration bit the interface can be configured in full-compliant mode (default): in this mode the value returned as response to a read operation will be properly masked in order to set reserved bits to 0, as from specification. this operation is performed on all registers included the standard or extended audio address space. if the full-compliant mode is not selected the full 16 bits data from the cor- responding ram register will be returned with no further manipulation. if an odd-addressed register reading operation is performed the following scheme is adopted: ? slot 0: report valid bit set to 1 for both slot 1 and slot 2 ? slot 1 (address): report the odd address ? slot 2 (data): report all 0s 2.2 writing ac `97 registers when a write operation into one of the available ac`97 registers is performed the entire 16 bits data word is written into the related ram register (also reserved bits are passed through). some bits of some register may have a corresponding hardware register (flip-flop) , used to control the internal status of the device: in this case the value of the ff is also updated every time a write to the related ram register is performed. the status of these ff is reverted to their default values after a hardware reset or a software reset (writing to reg. 00h) request has been issued; as a consequence also the dsp will have to reset the ram register contents. some register may have a different behaviour from the one depicted above. here is a brief summary of those registers. ? regs. 7ch and 7eh: these are the vendor id1 and id2 registers. any write request to one of these will be ignored. ? regs. 28h: the extended audio id register is read only. therefore any write request will be ignored. ? regs. 26h: when a write request is issued the actual data written into the ram register is xxxxxxxxxxxx1110, where x stands for the incoming data. ? regs. 2ah: when a write request is issued the actual data written into the ram register is xxxxxx0111xxxxxx, where x stands for the incoming data. ? regs. 32h and 34h: any write request into one of these adc sample rate register will result in the value bb80h written into the corresponding ram register.
STA304 8/30 3.0 i2s input interface configuration in order to configure the i2s input interface the configuration register b ( crb ) can be used. using the 3 i2si_align_x bits one of 6 configuration mode can be selected. following is a table describing each one of them. by default standard i2s input interface slave is provided (mode 1 in bits 0,1,2 of register crb, i 2 s_bick_pol = 1 and i2si_lrck_pol = 0 with some register) 3.1 switching characteristics (10 pf load; fsm=32 khz to 96khz): figure 2. mode # of slots w. lenght alignment delay slot notes 0 32 24 left no 1 32 24 left yes 2 32 16 right no msb first only 3 32 24 right no 4 24 24 left no slave only 5 not valid not valid not valid not valid reserved, do not use. 6 24 16 right no msb first only. slave only 7 24 24 right no slave only bicki frequency (master mode): (slave mode): 3.072mhz max 6.4 mhz bicki pulse width low (t 0 ) (slave mode): min 40 ns. bicki pulse width high (t 1 ) (slave mode): min 40 ns. bicki active to lrcki edge delay (t 2 ): min 20 ns. bicki active to lrcki edge setup (t 3 ): min 20 ns. sdi valid to bicki active setup (t 4 ): min 20 ns. bicki active to sdi hold time (t 5 ): min 20 ns. bicki falling to lrcki edge (t 6 ) (master mode): min 3 ns; max 9 ns. t 2 t 3 t 0 t 1 t 5 t 4 t 6 d00au1244 lrcki bicki sdi
STA304 9/30 4.0 i2s output interface configuration in order to configure the i2s output interface the configuration register b ( crb ) can be used. using the 3 i2so_align_x bits one of 6 configuration mode can be selected. following is a table describing each one of them. by default standard i2s output interface master is provided (mode 1 in bits 8,9,10 of register crb, i2so_bick_pol = 1 and i2so_lrck_pol = 0 in the same register) 4.1 switching characteristics (10 pf load; fsm=48 khz): figure 3. mode # of slots w. lenght alignment delay slot notes 0 32 24 left no 1 32 24 left yes 2 32 16 right no msb first only 3 32 24 right no 4 24 24 left no slave only 5 not valid not valid not valid not valid reserved, do not use. 6 24 16 right no msb first only. slave only 7 24 24 right no slave only scko frequency (master mode): 64 fsm (slave mode): 64 fsm scko pulse width low (t 0 ) (slave mode): min 40 ns. scko pulse width high (t 1 ) (slave mode): min 40 ns. scko active to lrcko edge delay (t 2 ): min 20 ns. scko active to lrcko edge setup (t 3 ): min 20 ns. sdo valid to scko active setup (t 4 ): min 20 ns. scko active to sdo hold time (t 5 ): min 20 ns. scko falling to lrcko edge (t 6 ) (master mode): min 2 ns; max 8 ns. scko falling to sdo edge(t 7 ) (master mode): min 2 ns; max 8 ns. (slave mode): min 6 ns; max 17 ns t 2 t 3 t 0 t 1 t 5 t 7 t 4 t 6 d00au1245 lrcko bicko sdo
STA304 10/30 5.0 ddx output switching the 5 ddx output (l,r,sl,sr,lfe) are ternary modulated pwm, designed to drive directly sta50x power bridge ics or any custom discrete power. the pwm output frame is delayed from channel to channel in order to reduce the crosstalk at the stereo sta50x device at low audio dynamics. the pwm order in the STA304 is: Cl Cls Cr Crs with 32 ticks (of master clock) or ~640ns between the beginning of each pwm frame (frame period is ~2.6usec). the lfe pwm signal is independently generated (synchronous with ls pwm output), because it is intended to be used alone on a mono-configured sta50x ic (no crosstalk issues). in this way the low-modulated level pwm signal of different channels switches when the others are at zero level, so when the output power is in dump state (both terminals of the speaker loads are connected to ground), caus- ing no noise cross-injection. best performances are obtained when only front channels (l/r) or rear channels (sl/sr) are fed to a single sta50x device, because the pwm frames of l an r have the maximum distance of ~1.3usec (same for sl and sr). of course crosstalk is anyway removed with a good power supply design/layout for sta50x ics (low impedance stage and low inductance loop between powervdd and gnd). see application notes for more details
STA304 11/30 6.0 sample rate converter the sample rate converter resamples the selected input data source in order to send to the dsp an audio stream with a fixed frequency of 48 khz. the following picture show the basic architecture. figure 4. the selection between x2 fir interpolation or direct antialiasing filter on input data is made automatically by the threshold selector block. if the input sampling frequency (measured by drll) is high than the src threshold (see table 2 section 12.9), the direct antialising filter is selected, otherwise if the input frequency is lower than the src threshold, the x2 fir filter is added the data path. a 1khz hysteresis is fixed around the src threshold nominal values of tab. 2 section 12.9, to prevent unstable oscillations. in figure 5 the drll lock phase is shown for 32khz,44.1khz, 48khz and 96khz input frequency. note that only after this phase (including the flat part of the graph) the src performances are in spec. figure 5. drll lock delay interpolation fir x2 anti-alias filt interpolation fir x2 2xfs fs fs data_in sinc 6 async. drll lrck_in thresh. selector ratio 4xfs or 2xfs data_out 48khz 0 0.05 0.1 0.15 0.2 0.25 0 1 2 3 4 5 6 7 8 9 10 x 10 4 second esimated frequency
STA304 12/30 7.0 dap input stage the device provides 3 mutually exclusive input interfaces: i2s, s/pdif and ac`97. hereby is a small description of the characteristics for each of them and a table showing how to select it. figure 6. 7.1 input from i 2 s using this input interface a maximum of 4 channels can be sent to the dsp. as detailed in the related paragraph this i/f can be configured both as master or slave. when in master the sampling frequency is fixed to 48 khz and the src can be bypassed using the src_bypass configuration bit (in cra register). if slave operation is selected the full range between 32khz and 96khz is supported but the src must always be in the processing path (no bypass). in order to select this interface the ac97_mode pin must be tied to gnd and the i2s_spdif_sel bit must be 0. this input configuration requires that sa pin (#11) is connected to ground 7.2 input from s/pdif this interface is compliant with the aes/ebu iec 958, s/pdif and eiaj cp-340/1201 professional and con- sumer standards. the full range from 32 khz up to 96 khz is supported but the src bypass option must be switched off. using the spdif_mode bit this interface can be configured as digital or analog input. if the analog mode is selected the line receiver can decode differential as well as single ended inputs. the receiver consists of a differential input schmitt trigger comparator with 50 mv of hysteresis, which prevents noisy signals from corrupting the data recovered. the minimum input differential voltage is 200 mv. if the digital mode is selected only the single ended operation is supported; the input signal should be cmos compliant. in order to select this interface the ac97_mode pin must be tied to gnd and the i2s_spdif_sel must be 1. this input configuration requires that sa pin (#11) is connected to ground 7.3 input from ac`97 in order to select this interface the ac97_mode pin must be tied to vdd (i2s_spdif_sel bit is dont care). the ac`97 interface can be configured either as primary or secondary device using the external configuration pin sa. yram src ac97 i2s s/pdif left right sl/center sr center lfe ac97_sel i2s_spdif_sel src_bypass pll mck pll_factor pll_bypass xti dsp ddx i2s i2c yram left right sl/center sr center lfe /1024 /2 or /8 lrck ck_out lrck
STA304 13/30 this interface support 4 sampling frequencies, according to the variable and double rate audio codec `97 specification. the following table summarize the slot usage for each one the these frequencies: * slots 3, 4 and 6 are always requested. slots 10, 11 and 12 are requested only when needed. the following table summarize the different input possibilities: * in this configuration the bypass is always active, regardless src_bypass bit in reg. 5ah 8.0 pll in order to generate the internal 49.152 mhz clock a low-jitter pll has been included in the device. it can be config- ured to work either with a multiplication factor of x8 or x2, in order to fit an external frequency reference of 6.144 mhz or, respectively, 24.576 mhz. this could be useful when the device is configured to work in ac`97 slave mode where the master clock is 24.576 mhz. to select the multiplication factor the pll_factor bit can be used . using the pll_bypass bit the pll section can be bypassed, allowing direct connection of the internal clock to the xti pin. when this option is selected an external frequency of 49.152 mhz should be provided to the device. in this condition the pll is automatically powered-down. 9.0 powerdown management the powerdown capability and its logic behaviour is shown in figure 7 - powerdown management . basically there are three powerdown requests which comes from the extern of the device and will cause a different pow- erdown condition: - external pwdn pin C this signal will turn-off the device which, as a consequence, will enter the power- down mode (all the device clocks are stopped). the device will exit this state as soon as the pwdn pin is deasserted. - pr5 bit (reg. 26h, bit 13) C setting this bit will cause a partial powerdown of the device: infact all the clocks will be suspended, except that used to keep the ac97 and i2c cells alive. in this way, using either of these input interfaces, itll be possible to resume from this state simply resetting the pr5 bit. - eapd bit (reg.26h, bit 15) C the external amplifier powerdown bit controls the state of the related pin (eapd) which, in turn, is used to switch off the external power chip. freq. slot 3 slot 4 slot 6 slot 7 slot 8 slot 9 slot 10 slot 11 slot 12 48 left right center surr.l surr.r lfe 44.1 left right surr.l surr.r 88.2 * left right center left (n+1) right (n+1) center (n+1) 96 left right center left (n+1) right (n+1) center (n+1) input from channels available freq. (khz) bypass notes i2s (master) 4 48 yes bypass is user selectable i2s (slave) 4 32..96 no s/pdif 2 32..96 no ac`97 6 48 yes * left, right, sl, sr, center, lfe ac`97 3 96 no left, right, center ac`97 4 44.1 (vra) no left, right, sl, sr ac`97 3 88.2 (vra) no left, right, center
STA304 14/30 figure 7. powerdown management in order to avoid any possible pop-noise while switching between the various powerdown modes a particular masking technique has been adopted to drive the actual controlling signals: as shown in the above figure the 3 powerdown requests will inform the dsp using the related bits in specific registers. after that the dsp performs a software fade-out of the channels volume and, finally, activates the mute flags of the various channels. the actual controlling lines are the result of a logical and operation between the relative request signals and the 4 channel mute bits (lr, lfe, sl and sr). moreover the external power chip will be turned off (via the eapd pin) not only as a consequence of an eapd request, but also as a consequence of a pr5 or pwdn requests: this solution will prevent any possible noise or glitch. & internal ck disable & chip powerdown & dsp requests or eapd (reg. 26h, bit 15) pwdn pin (reg.7efh, bit0) pr5 (reg.26h, bit 13) eapd pin (active low) (active low) lr lfe sl sr & lr reg. 02h bit 15 lfe reg. 36h bit 15 sr reg. 38h bit 07 sl reg. 38h bit 15
STA304 15/30 10.0 bass managementand eq the STA304 has the ability to redirect the sound to the sbw channel and to pass each channel through a 4- stage cascaded 2nd order iir filter. with the combination of the ddx gain/compressor (cra register bits 2-3) a dynamic eq can be implemented. beside that, a special side-firing sound can be achieved by enabling this feature available with the ready made filter topology on the surround channels. 10.1 bass redirection figure 8. there is an option to redirect each input channel to the sbw output channel. the scale factor of each channel should be set with values in the range of 0 (no redirection) to -1 (full redirection). about setting the scaling factors registers, see paragraph 10. the redirection is taking place when the bit 0 of the bass management register (add.72h) is set (see section 12.13). together with the static eq option (following section), by setting appropriate filters, a full bass management so- lution is available. (*) note: c and lfe channels are available only with 6 channels ac97 input. in case of 4 channels i 2 s, only l, r, ls, rs are available 10.2 static eq figure 9. phantom lr filter lr filter sur filter sur filter + scale l scale c scale r scale ls scale rs scale lfe sbw filter l c r ls rs lfe l r ls rs sbw ( iis c) (*) (*) scale in factor bi-quad0 bi-quad1 bi-quad2 bi-quad3 input output
STA304 16/30 each channel has a 4 stage cascaded 2nd order filter. the user can set each filter coefficients (see paragraph 10). the coefficient for the left and right channels are common, as well as the coefficients for the surrounds. there is also an input scaling factor for each channel which can be set with values from 0 to -1. the scaling factor should be set to an appropriate value that will prevent the filter going into saturation. the static eq filters are activated by setting static eq and side firing register (add. 70h, see section 12.12). 10.3 surround side firing instead of the normal filters described in the previous section above, a special topology is available for the sur- round channels: figure 10. by designing appropriate filters special surround sound can be achieved for a system which its surround speak- ers are located next to the front speakers and are rotated to the sides (see picture). the side firing topology is enabled by setting static eq and side firing register (add. 70h, see section 12.12). figure 11. speaker system with side-firing positioning scale in factor bi-quad0 bi-quad1 + and phase invering + left surround input left surround output bi-quad2 bi-quad3 scale in factor bi-quad0 bi-quad1 right surround input bi-quad2 bi-quad3 right surround output
STA304 17/30 11.0 coefficient handling in order to implement the static eq filters and the bass management, a ram space for user coefficients has been included in this device: starting from address 240h (yram) there are 69 x 20 bit registers available for this purpose. in order to be able to read or write into these registers an indirected addressing approach must be followed by the application software. as showed in figure 8 there are two ac'97 dedicated registers (4 x 8 bits registers from i2c point of view) to access the coefficient table. in register 78h (78h + 79h in i2c addressing) the 16 low bits of the coefficient are stored (by the user in case of a write operation, by the logic in case of a read operation); the higher 4 bits are stored in the lowest nibble of register 7ah (7bh in i2c addressing). the address of the coefficient on which the r/w operation must be performed is stored in the high byte of register 7ah. the address is made adding the coefficient index to the base location 40h. to select between read or write operation the 'r' bit in register 7ah (7bh in i2c addressing) must be properly setup. the actual read/write operation will start after the register 7ah (7bh in i2c addressing) has be written. the following paragraphs will explain this in more details. figure 12. coefficient registers usage 11.1 reading a coefficient value depending on the bus used to read the coefficient the following steps must be followed: ? reading from ac97 C write 8 bit index 40h and r/w bit at ac`97 address 7ah C read 16 lower data bits at ac`97 address 78h C read 4 higher data bits at ac`97 address 7ah ? reading from i 2 c C write 8 bit address at i2c address 7ah coeff index + 40h C write r/w bit at i 2 c address 7bh C read 8 middle data bits at i 2 c address 78h C read 8 lower data bits at i 2 c address 79h C read 4 higher data bits at i 2 c address 7bh 11.2 writing a coefficient value depending on the bus used to write the coefficient the following steps must be followed: ? writing from ac97 C write 16 lower bit data at ac`97 address 78h C write 8 bit index + 40h and r/w bit and 4 higher data bits at ac`97 address 7ah ? writing from i2c C write 8 middle data bits at i2c address 78h C write 8 lower data bits at i2c address 79h C write 8 bit address at i2c address 7ah coeff index + 40h C write 4 higher data bits and r/w bit at i2c address 7bh coefficient[15..0] coeff. address (8 bits) coefficient[19..16] r-x-x-x bit 0 bit 15 78h 7ah ac`97 78h 7ah i2c 79h 7bh r : set this bit to 1 for reading a coefficient, 0 for writing it.
STA304 18/30 11.3 coefficient map filter coefficients: chx0 = b2 chx1 = (b0)-1 chx2 = a2 chx3 = (a1)/2 chx4 = (b1)/2 index (decimal) index (hex) coefficient default value 0 0h 20 lr filter coef. lr00 (b2) 00000h 1 1h lr01 (b0-1) 00000h 4 4h lr04 (b1/2) 00000h 5 5h lr10 (b2) 00000h 19 13h lr34 (b1/2) 00000h 20 14h 20 surrounds filter coef. sur00 00000h 39 27h sur34 00000h 40 28h 20 sbw filter coef. sbw00 (b2) 00032h 41 29h sbw01 (b0-1) 80032h 42 2ah sbw02 (a2) 7c7eah 43 2bh sbw03 (a1/2) 81c6fh 44 2ch sbw04 (b1/2) 00032h 45 2dh sbw10 00000h 59 3bh sbw34 00000h 60 3ch 3 scale in factors -scale_in lr 80000h 61 3dh -scale_in sur 80000h 62 3eh -scale_in sbw 80000h 63 3fh 6 sbw redirection factors -scale_l ? sbw c0000h 64 40h -scale_r ? sbw c0000h 65 41h -scale_ls ? sbw c0000h 66 42h -scale_rs ? sbw c0000h 67 43h -scale_c ? sbw c0000h 68 44h -scale_lfe ? sbw 80000h
STA304 19/30 where ch stands for lr,sur or sbw and x stands for the filter number (0..3). the filter equation is yn = xn+((b0)-1)*xn + 2*((b1)/2)*xn-1 + b2*xn-2 - 2*((a1)/2)*yn-1 - a2*yn-2 = = b0*xn + b1*xn-1 + b2*xn-2 - a1*yn-1 - a2*yn-2 the coefficient registers are 20 bits wide and should be in the range [-1..1) (80000h to 7ffffh). scaling factor registers: for the filters xn = - (-scale_in) * chn , where chn is the value before scaling and xn is the input to the filter. for the sbw redirection sbwn = -s (-scale_ch)*chn the scaling factor registers are 20 bits wide and should be in the range [-1..0] (80000h to 00000h). sbw redirection: -1 for maximum redirection and 0 for no redirection. filter scaling: -1 for maximum input and 0 for no input to filter. 12.0 i 2 c bus specification the STA304 supports the i 2 c protocol. this protocol defines any device that sends data on to the bus as a trans- mitter and any device that reads the data as a receiver. the device that controls the data transfer is known as the master and the others as the slave. the master always starts the transfer and provides the serial clock for synchronisation. the STA304 is always a slave device in all its communications. 16bit registers are addressed as two 8 bit registers. the high byte has even address, while the low byte has odd address. for example, reading from register 02 (16bit) means read registers 02 (high byte) and 03 (low byte) from i 2 c. 12.1 communication protocol 12.1.1data transition or change data changes on the sda line must only occur when the scl clock is low. sda transition while the clock is high are used to identify start or stop condition. 12.1.2start condition start is identified by a high to low transition of the data bus sda signal while the clock signal scl is stable in the high state.a start condition must precede any command for data transfer. 12.1.3stop condition stop is identified by low to high transition of the data bus sda signal while the clock signal scl is stable in the high state. a stop condition terminates communications between STA304 and the bus master. 12.1.4acknowledge bit an acknowledge bit is used to indicate a successful data transfer. the bus transmitter, either master or slave, releases the sda bus after sending 8 bit of data. during the 9th clock pulse the receiver pulls the sda bus low to acknowledge the receipt of 8 bits of data. 12.1.5data input during the data input the STA304 samples the sda signal on the rising edge of the clock scl. for correct device operation the sda signal has to be stable during the rising edge of the clock and the data can change only when the scl line is low. 12.2 device addressing to start communication between the master and the STA304, the master must initiate with a start condition. following this, the master sends onto the sda line 8 bits (msb first) corresponding to the device select address
STA304 20/30 and read or write mode. the 7 most significant bits are the device address identifier, corresponding to the i 2 c bus definition. the STA304 i 2 c interface address is 0011110 . the 8th bit (lsb) is the read or write operation rw, this bit is set to 1 in read mode and 0 for write mode. after a start condition the STA304 identifies on the bus the device address and, if a match is found, it acknowledg- es the identification on sda bus during the 9th bit time. the following byte after the device identification byte is the internal space address. 12.3 write operation following a start condition the master sends a device select code with the rw bit set to 0. the STA304 ac- knowledges this and waits for the byte of internal address. after receiving the internal bytes address the STA304 again responds with an acknowledge. 12.3.1byte write in the byte write mode the master sends one data byte, this is acknowledged by STA304. the master then ter- minates the transfer by generating a stop condition. 12.3.2multibyte write the multibyte write mode can start from any internal address. the transfer is terminated by the master gener- ating a stop condition. figure 13. write mode sequence figure 14. read mode sequence dev-addr ack start d98au825b rw sub-addr ack data in ack stop byte write dev-addr ack start rw sub-addr ack data in ack stop multibyte write data in ack dev-addr ack start d98au826a rw data no ack stop current address read dev-addr ack start rw sub-addr ack dev-addr ack stop random address read data no ack start rw dev-addr ack start data ack data ack stop sequential current read data no ack dev-addr ack start rw sub-addr ack dev-addr ack sequential random read data ack start rw data ack no ack stop data rw= high
STA304 21/30 13.0 register summary 13.1 reset register (add. 00h) writing any value to this register performs a register reset, which causes all registers to revert to their default values. reading this register returns 00e4h as it is the id code of the part and its 3d stereo enhancement type (see ac'97 revision 2.1 specification, section 6.3.1). 13.2 lr volume register (add. 02h) this register manage the stereo (both right and left channels) output signal volumes. the msb of the register is the mute bit. when this bit is set to 1 the level for that channel is set at - db. ml6 through ml0 is for the left channel level, mr6 through mr0 is for the right channel. there are two options: in 'full compliance' operating mode (bit 0 in the cra register, address 5ah, is set to '0') only 6 bits are active (mx0 to mx5) and each step corresponds to 1.5 db. in 'proprietary' mode (bit 0 in the cra register is set to '1') mx0 to mx6 can have the values between 0h to 68h (110 1000) and each step corresponds to 1db. greater values are undefined. the default value is 8000h (1000 0000 0000 0000), which corresponds to 0 db attenuation with mute on. 'full compliance' mode 'proprietary' mode d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0000000111001 0 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute ml6 ml5 ml4 ml3 ml2 ml1 ml0 x mr6 mr5 mr4 mr3 mr2 mr1 mr0 mute mx6mx0 function 0 x00 0000 0 db attenuation 0 x01 1111 46.5db attenuation 0 x11 1111 94.5db attenuation 1 xxx xxxx db attenuation mute mx6mx0 function 0 000 0000 0 db attenuation 0 001 1111 31db attenuation 0 011 1111 63db attenuation ... 0 110 0001 97 db attenuation 0 110 0010 99db attenuation 0 110 0011 100db attenuation 0 110 0100 102db attenuation 0 110 0101 104db attenuation 0 110 0110 107db attenuation 0 110 0111 111db attenuation 0 110 1000 db attenuation 1 xxx xxxx db attenuation
STA304 22/30 13.3 tone control register (add. 08h) this register support tone controls (bass and treble). the step size is 2db. writing a 0000h corresponds to +12db of gain. center frequencies (from which gains are measured) are 160hz for bass and 5,000hz for treble. the default value is 0f0fh, which corresponds to bypass of bass or treble gain. the tone feature is implemented only on the l and r front channel. 13.4 powerdown ctrl/staus register (pcsr) : add. 26h note: bits d0..d3 will be masked to the showed value before writing into the ram registers, other bits will simply pass through . d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 xxxxba3ba2ba1ba0xxxxtr3tr2tr1tr0 tr3... tr0 or ba3... ba0 function 0000 +12 db of gain 0001 +10 db of gain 0010 +8 db of gain 0011 +6 db of gain 0100 +4 db of gain 0101 +2 db of gain 0110 +1 db of gain 0111 0 db of gain 1000 -1 db of gain 1001 -2 db of gain 1010 -4 db of gain 1011 -6 db of gain 1100 -8 db of gain 1101 -10 db of gain 1110 -12 db of gain 1111 bypass d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 eapd pr5pr4 1110 bit r/w rst name description 12 r/w 0 pr4 setting this bit to 1 the bit_clk and the sdata_in signal will be fixed to the digital low level. to resume the normal operation either an hardware reset or a softreset must be performed. 13 r/w 0 pr5 in order to set the device in a powerdown-like condition this bit must be set to 1. this will stop the device internal clock: only the pll and ac`97, i 2 c clocks will still be running. dsp should start power-down sequence in order to accomplish this request. 15 r/w 1 eapd the value of this bit should be checked by the dsp in order to recognize an external power amplifier power-down request. as a consequence the dsp should start the power-down sequence (volume fade-out)
STA304 23/30 13.5 extended audio id register (add. 28h) the extended audio id is a read only register that identifies which extended audio features are supported (see ac'97 revision 2.1 specification, section a.2.1). the extended features supported are variable rate pcm audio (vra), double- rate pcm audio (dra), pcm center (cdac), pcm surround (sdac) and pcm lfe (ldac). codec_id0 report the status of sa pin. codec_id1 always report 0. hence, the configurations are primary (00) if sa pin is 0 or secondary (01) if sa pin is 1. 13.6 extended audio status and control register (add. 2ah) ? vra= 1 enables variable rate audio mode (sample rate control registers and slotreq signaling) ? dra= 1 enables double- rate audio mode bits d9- d6 are read only status of the extended audio feature readiness. when a write request is issued the actual data written into the ram register is 'xxxxxx0111xxxxxx'. for more details refer to ac97 rev 2.1, section a.2.2 13.7 audio sample rate control registers (add. 2ch - 34h) in vra mode, two frequencies are supported 48000(bb80h) hz and 44100(ac44h) hz. if one of these value written to the 2ch register, that value will be echoed back when read, otherwise the closest (higher in case of a tie) sample rate supported is returned. the content of 2eh and 30h registers is copied from the 2ch register. if the double rate audio (dra) mode is active, the sample rate programmed will be multiplied by 2x. for ex- ample: when running at 88.2 khz, the dra bit will be programmed to 1, and the sample rate programmed would be 44.100. the default value after cold or warm register reset for these registers (bb80h) is 48 khz. the content of the adc sample rate registers (32h and 34h) stays always bb80h. 13.8 6-channel volume control register (add. 36h - 38h) these read/write registers control the output volume of the optional four pcm channels, and values written to the fields behave the same as the play master volume register (index 02h), which offers attenuation but no gain. there is an independent mute (1= on) for each channel. the default value after reset for this registers (8080h) corresponds to 0 db attenuation with mute on. d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1 d0 0id00000011100001 1 d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1 d0 0111 dravra d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute lfe6 lfe5 lfe4 lfe3 lfe2 lfe1 lfe0 mute cnt6 cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 mute lsr6 lsr5 lsr4 lsr3 lsr2 lsr1 lsr0 mute rsr6 rsr5 rsr4 rsr3 rsr2 rsr1 rsr0
STA304 24/30 13.9 configuration register a (cra) : add. 5ah note: in test_mode -> pll_bypass = 0. table 1. src threshold d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 src_by pass drll_d bg src_th r_1 src_th r_0 spdif_ mode i2s_sp dif_sel mckou t_mode pll_by pass pll_fac tor ddx_p wrmode ddx_zd _enable ddx_rst ddx_ga in_1 ddx_ga in_0 i2si_dbu ff_mode ac97_f c_mode bit r/w rst name description 0 r/w 0 ac97_fc_mode ac97 full compliant mode (0 to enable). when in fc mode any read of registers will return only valid bits: bits marked as reserved by ac97 v2.0 specification will return 0, regardless of the ram contents. 1 r/w 0 i2si_dbuff_mode enable doublebuffer mode for the i2s input interface (write1 to enable this option) . this is strongly required if this interface is operated in slave mode at 48khz, synchronous with the input source. in this condition also sample rate converter bypass is suggested to omprove performances. 2 r/w 0 ddx_gain_0 ddx gain setting (lsb/msb). these two bits, concatenated, will set the ddx stage gain and the compression as shown in table 1. 3 r/w 0 ddx_gain_1 4 r/w 1 ddx_rst ddx reset (active high) 5 r/w 1 ddx_zd_enable ddx zero detect feature. if this bit is 1 the feature is enabled. 6 r/w 1 ddx_pwrmode ddx power mode (truth table). using this bit it is possible to select the truth table used by the ddx digital output stage (1 = st standard) 7 r/w 0 pll_factor pll factor (x2 or x8). it should be used according to the input frequency provided to the device: 1 (x8) when 6.144 mhz are provided, 0 (x2) when 24.576 mhz. 8 r/w 1 pll_bypass pll bypass. setting this bit to 0 will bypass the pll; internal master clock will be directly connected to xti pin. 9 r/w 0 mckout_mode mckout mode: 12.288 mhz (1) or 24.576 mhz (0). 10 r/w 0 i2s_spdif_sel i2s - s/pdif selector. select the input source: set to 0 for i2s input, 1 for s/pdif input. 11 r/w 0 spdif_mode s/pdif mode. set to 0 to select analog mode, 1 to select digital mode. 12 r/w 1 src_thr_0 sample rate threshold (lsb/msb). these bits are used to select the threshold frequency enabling the src anti-alias filter. 13 r/w 0 src_thr_1 table 2 shows the threshold selections. 14 r/w 0 drll_dbg drll debug mode. when this mode is activated (1) the drll digital ratio is latched on the output channels instead of the audio data. 15 r/w 0 src_bypass src bypass. setting this bit to 1 the src block can be bypassed and the selected input i/f is directly connected to the dsp. src_thr_0 src_thr_1 threshold frequency 0 0 inactive 0 1 58.875 to 61.125khz 1 0 78.973 to 81.000khz 1 1 always active
STA304 25/30 table 2. ddx gain ddx gain compression since a full-scale output of the gc/vol block is mapped to full output modulation, any signal exceeding 0 dbfs at the output of the gc/vol block will be clipped. the purpose of the compression algorithm is to reduce the gain of the system when 0 dbfs has been exceeded such that clipping does not take place, thus performing an output limiting function. this would yield a constant vout once the gained input exceeds 0 dbfs. with ddx_gain_0 = 1, the output of the gc/vol block is compared to a threshold set just below 0 dbfs. when the output of gc/vol exceeds this threshold the gain of system is reduced following a set time-constant and gain-reduction rate. this reduction in gain is stored as a variable. if subsequently the output of gc/vol remains below a separate lower threshold for a set amount of time the gain is then increased following another time- constant and gain rate. thus, seven different constants determine the attack, release, and limiting characteris- tics of the compression algorithm. these constants have been tuned to sound as musical as possible when the dynamic range of a recording is being reduced due to 0 dbfs being exceeded. figure 15. compression response to 500 hz sine at 0 dbfs with gain of +10 db ddx_gain_0 ddx_gain_1 ddxgain ddx compression 001x no 012x no 1 0 2x yes 1 1 3x yes
STA304 26/30 13.10configuration register b (crb) : add. 5ch note: power-on default values will configure serial input interface as i2s slave and the output interface as i2s master. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i2so_m sblsb i2so_lr ck_master i2so_lr ck_pol i2so_bc k_master i2so_bi ck_pol i2so_ali gn_2 i2so_ali gn_1 i2so_ali gn_0 i2si_ms blsb i2si_lr ck_master i2si_lr ck_pol i2si_bc k_master i2si_bic k_pol i2si_alig n_2 i2si_alig n_1 i2si_alig n_0 bit r/w rst name description 0 r/w 1 i2si_align_0 i2s (input) alignement. using these bits the word alignement can be adjusted with respect to the lrck edges. please refer to the related paragraph for more details. the default value is mode 1. 1 r/w 0 i2si_align_1 2 r/w 0 i2si_align_2 3 r/w 1 i2si_bick_pol i2s (input) bick polarity. this bit should be configured according to the used serial protocol. in order to sample incoming data on the rising edge (data changes on the falling edge) this bit should be set to 1. set to 0 to reverse the sampling edge. 4 r/w 0 i2si_bck_master i2s (input) master/slave selection. the i2s input interface can be configured as both master or slave: if the master mode is selected (1) the bick line will be an output (64 x 48khz fixed). otherwise (0) slave mode is selected and this line is an input. 5 r/w 0 i2si_lrck_pol i2s (input) lrck polarity. set to 0 to receive left samples when lrck is low, 1 otherwise. 6 r/w 0 i2si_lrck_master i2s (input) master/slave selection. the i2s input interface can be configured as both master or slave: if the master mode is selected (1) the lrck line will be an output (48khz fixed). otherwise (0) slave mode is selected and this line is an input (continuous frequency between 32khz and 96khz). 7 r/w 1 i2si_msblsb i2s (input) msb/lsb selection. use this bit to select how the sample word is received by the i2s input interface: set to 0 to configure as lsb first, 1 msb first. 8 r/w 1 i2so_align_0 i2s (output) alignemt. using these bits the word alignement can be adjusted with respect to the lrck edges. please refer to the related paragraph for more details. the default value is mode 1. 9 r/w 0 i2so_align_1 10 r/w 0 i2so_align_2 11 r/w 1 i2so_bick_pol i2s (output) bick polarity. this bit should be configured according to the used serial protocol. in order to sample outcoming data on the rising edge (data changes on the falling edge) this bit should be set to 1. set to 0 to reverse the sampling edge. 12 r/w 1 i2so_bck_master i2s (output) master/slave selection. the i2s output interface can be configured as both master or slave: if the master mode is selected (1) the bick line will be an output (64 x 48khz fixed). otherwise (0) slave mode is selected and this line is an input. 13 r/w 0 i2so_lrck_pol i2s (output) lrck polarity. set to 0 to transmit left samples when lrck is low, 1 otherwise. 14 r/w 1 i2so_lrck_master i2s (output) master/slave selection. the i2s output interface can be configured as both master or slave: if the master mode is selected (1) the lrck line will be an output. otherwise (0) slave mode is selected and this line is an input. in any case the frequency is fixed at 48 khz 15 r/w 1 i2so_msblsb i2s (output) ) msb/lsb selection. use this bit to select how the sample word is transmitted by the i2s output interface: set to 0 to configure as lsb first, 1 msb first.
STA304 27/30 13.11phantom center register (add. 60h) setting bit 0 enables the phantom center channel feature. when this feature is on, the content of the center channel is split and added to the l and r channels. 13.12static eq and side firing register (add. 70h) this register controls the activation of the static eq and the side firing surround sound. for more information on setting eq parameters, see paragraph 9 .2 13.13bass management register (add. 72h) setting bit 0 activate the bass management. for more information on bass management, see paragraph 9 .1. default is 0h. 13.14bypass register (add. 74h) setting bit 0 bypass the dsp block. all channels are bypassed and output equal to input, regardless of all other algorithm register settings (volume, tone, phantom, eq). default is 0h d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 phantom d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 eq1 eq0 eq1 eq0 0 0 eq off (default) 0 1 eq enabled 1 x side firing + eq d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 bass mng d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 bypass
STA304 28/30 13.15bist and status register (basr) : add. 76h 13.16coefficients handling registers (add. 78h C 7ah) see paragraph 10. 13.17vendor id registers (add. 7ch C 7eh) these registers are specific vendor identification for the STA304. the microsofts plug and play vendor id code is "alj". the r ev7.. 0 field is for the vendor revision number. these are read only registers, any write request to one of these will be ignored. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dsp_bis t_start dsp_bis t_running dsp_bis t_stop dsp_ra m x x src_sp ram_2 src_sp ram_1 ddx_dp ram ddx_sp ram_3 ddx_sp ram_2 ddx_sp ram_1 bist_st op bist_st art spdif_ status src_st atus bit i/f dsp rst name description 0 r 1 src_status when 0, the digital pll in the src is locked. when 1 the digital pll is out of lock. 1 r 1 spdif_status when 1, the spdif interface is out of lock. when 0 the interface is locked to the spdif stream input. 2 w r 0 bist_start reserved 3 r 0 bist_stop reserved 4 r 0 ddx_spram_1 reserved 5 r 0 ddx_spram_2 reserved 6 r 0 ddx_spram_3 reserved 7 r 0 ddx_dpram reserved 8 r 0 src_spram_1 reserved 9 r 0 src_spram_2 reserved 10 r/w 1 ac3_amen enable automuting if ac3 frame header found 11 r/w 0 ch1_amen enable automuting if no ch1_status bit found 12 r r 0 dsp_ram reserved 13 r r 0 dsp_bist_stop reserved 14 r r 0 dsp_bist_running reserved 15 w r 0 dsp_bist_start reserved d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1 d0 c15c14c13c12c11c10c9c8c7c6c5c4c3c2c1 c0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w c19 c18 c17 c16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0100000101001 1 0 0 01001010 rev7 rev6 rev5 rev4 rev3 rev2 rev1 rev0
29/30 STA304 tqfp44 (10 x 10) dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.014 0.018 c 0.09 0.20 0.004 0.008 d 12.00 0.472 d1 10.00 0.394 d3 8.00 0.315 e 0.80 0.031 e 12.00 0.472 e1 10.00 0.394 e3 8.00 0.315 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0 (min.), 3.5?(typ.), 7 (max.) a a2 a1 b seating plane c 11 12 22 23 33 34 44 e1 e d1 d e 1 k b tqfp4410 l 0.10mm .004 outline and mechanical data
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